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M95256 M95128
256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
PRELIMINARY DATA
s s s s
SPI Bus Compatible Serial Interface Supports Positive Clock SPI Modes 5 MHz Clock Rate (maximum) Single Supply Voltage: - 4.5V to 5.5V for M95xxx - 2.7V to 3.6V for M95xxx-V - 2.5V to 5.5V for M95xxx-W - 1.8V to 3.6V for M95xxx-R
8 1
PSDIP8 (BN) 0.25 mm frame
14 1
TSSOP14 (DL) 169 mil width
s s
Status Register Hardware and Software Protection of the Status Register BYTE and PAGE WRITE (up to 64 Bytes) Self-Timed Programming Cycle Resizeable Read-Only EEPROM Area Enhanced ESD Protection 100,000 Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
s s s s s s
8 1
SO8 (MN) 150 mil width
8 1
SO8 (MW) 200 mil width
DESCRIPTION These SPI-compatible electrically erasable programmable memory (EEPROM) devices are organized as 32K x 8 bits (M95256) and 16K x 8 bits (M95128), and operate down to 2.7 V (for the
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C D Q Serial Clock Serial Data Input Serial Data Output
D C S W M95xxx
Q
S
W HOLD VCC VSS
Chip Select
HOLD
Write Protect Hold Supply Voltage Ground
VSS
AI01789C
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M95256, M95128
Figure 2A. DIP Connections Figure 2C. TSSOP Connections
M95128 M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790C
VCC HOLD C D
S Q NC NC NC W VSS
1 2 3 4 5 6 7
14 13 12 11 10 9 8
AI02346
VCC HOLD NC NC NC C D
Note: 1. NC = Not Connected
Figure 2B. SO Connections -V version), 2.5 V (for the -W version), and down to 1.8 V (for the -R version of each device). The M95256 and M95128 are available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Outline packages. Each memory device is accessed by a simple serial interface that is SPI bus compatible. The bus signals are C, D and Q, as shown in Table 1 and Figure 3. The device is selected when the chip select input (S) is held low. Communications with the chip can be interrupted using the hold input (HOLD).
M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01791C
VCC HOLD C D
Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VO VI VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Output Voltage Range Input Voltage Range Supply Voltage Range Electrostatic Discharge Voltage (Human Body model) 2 PSDIP8: 10 sec SO8: 40 sec TSSOP14: t.b.c. Value -40 to 125 -65 to 150 260 215 t.b.c. -0.3 to VCC+0.6 -0.3 to 6.5 -0.3 to 6.5 4000 Unit C C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
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M95256, M95128
Figure 3. Microcontroller and Memory Devices on the SPI Bus
SPI Interface with SDO (CPOL, CPHA) = SDI ('0', '0') or ('1', '1') SCK Master (ST6, ST7, ST9, ST10, Others)
CQD M95xxx
CQD M95xxx S
CQD M95xxx S
CS3
CS2
CS1
S
AI01958C
SIGNAL DESCRIPTION Serial Output (Q) The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. Serial Input (D) The input pin is used to transfer data serially into the device. Instructions, addresses, and the data to be written, are each received this way. Input is latched on the rising edge of the serial clock. Serial Clock (C) The serial clock provides the timing for the serial interface (as shown in Figure 4). Instructions, addresses, or data are latched, from the input pin, on the rising edge of the clock input. The output data on the Q pin changes state after the falling edge of the clock input. Chip Select (S) When S is high, the memory device is deselected, and the Q output pin is held in its high impedance state. Unless an internal write operation is underway, the memory device is placed in its stand-by power mode. After power-on, a high-to-low transition on S is required prior to the start of any operation. Write Protect (W) The protection features of the memory device are summarized in Table 3. The hardware write protection, controlled by the W pin, restricts write access to the Status Register
(though not to the WIP and WEL bits, which are set or reset by the device internal logic). Bit 7 of the status register (as shown in Table 5) is the Status Register Write Disable bit (SRWD). When this is set to 0 (its initial delivery state) it is possible to write to the status register if the WEL bit (Write Enable Latch) has been set by the WREN instruction (irrespective of the level being applied to the W input). When bit 7 (SRWD) of the status register is set to 1, the ability to write to the status register depends on the logic level being presented at pin W: - If W pin is high, it is possible to write to the status register, after having set the WEL bit using the WREN instruction (Write Enable Latch). - If W pin is low, any attempt to modify the status register is ignored by the device, even if the WEL bit has been set. As a consequence, all the data bytes in the EEPROM area, protected by the BPn bits of the status register, are also hardware protected against data corruption, and appear as a Read Only EEPROM area for the microcontroller. This mode is called the Hardware Protected Mode (HPM). It is possible to enter the Hardware Protected Mode (HPM) either by setting the SRWD bit after pulling low the W pin, or by pulling low the W pin after setting the SRWD bit. The only way to abort the Hardware Protected Mode, once entered, is to pull high the W pin. If W pin is permanently tied to the high level, the Hardware Protected Mode is never activated, and
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M95256, M95128
Figure 4. Data and Clock Timing
CPOL CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
the memory device only allows the user to protect a part of the memory, using the BPn bits of the status register, in the Software Protected Mode (SPM). Hold (HOLD) The HOLD pin is used to pause the serial communications between the SPI memory and controller, without losing bits that have already been decoded in the serial sequence. For a hold condition to occur, the memory device must already have been selected (S = 0). The hold condition starts when the HOLD pin is held low while the clock pin (C) is also low (as shown in Figure 5). During the hold condition, the Q output pin is held in its high impedance state, and the levels on the input pins (D and C) are ignored by the memory device. It is possible to deselect the device when it is still in the hold state, thereby resetting whatever transfer had been in progress. The memory remains in the hold state as long as the HOLD pin is low. To restart communication with the device, it is necessary both to remove the hold condition (by taking HOLD high) and to select the memory (by taking S low).
OPERATIONS All instructions, addresses and data are shifted serially in and out of the chip. The most significant bit is presented first, with the data input (D) sampled on the first rising edge of the clock (C) after the chip select (S) goes low. Every instruction starts with a single-byte code, as summarized in Table 4. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S held low). If an invalid instruction is sent (one not contained in Table 4), the chip automatically deselects itself. Write Enable (WREN) and Write Disable (WRDI) The write enable latch, inside the memory device, must be set prior to each WRITE and WRSR operation. The WREN instruction (write enable) sets this latch, and the WRDI instruction (write disable) resets it. The latch becomes reset by any of the following events: - Power on - WRDI instruction completion - WRSR instruction completion - WRITE instruction completion.
Table 3. Write Protection Control on the M95256 and M95128
W 0 or 1 1 0 SRWD Bit 0 1 1 Data Bytes Mode Software Protected (SPM) Hardware Protected (HPM) Status Register Protected Area Writeable (if the WREN instruction has set the WEL bit) Hardware write protected Software write protected by the BPn of the status register Hardware write protected by the BPn bits of the status register Unprotected Area Writeable (if the WREN instruction has set the WEL bit) Writeable (if the WREN instruction has set the WEL bit)
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M95256, M95128
Figure 5. Hold Condition Activation
CLOCK
HOLD PIN
MEMORY STATUS
ACTIVE
HOLD
ACTIVE
HOLD
ACTIVE
AI02029B
Figure 6. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register Status Register An - 63 An Size of the Read only area of the EEPROM
Y Decoder
64 Bytes
0000h
003Fh
X Decoder
AI02030B
Note: 1. The cell An represents the byte at the highest address in the memory
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M95256, M95128
Table 4. Instruction Set
Instruc tion WREN WRDI RDSR WRSR READ WRITE Description Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Table 5. Status Register Format
b7 SRWD X X X BP1 BP0 WEL b0 WIP
Note: 1. SRWD, BP0 and BP1 are Read and write bits. 2. WEL and WIP are Read only bits.
As soon as the WREN or WRDI instruction is received, the memory device first executes the instruction, then enters a wait mode until the device is deselected. Read Status Register (RDSR) The RDSR instruction allows the status register to be read, and can be sent at any time, even during a Write operation. Indeed, when a Write is in progress, it is recommended that the value of the Write-In-Progress (WIP) bit be checked. The value in the WIP bit (whose position in the status register is shown in Table 5) can be continuously polled, before sending a new WRITE instruction, using the timing shown in Figure 7. The Write-InProcess (WIP) bit is read-only, and indicates whether the memory is busy with a Write operation. A '1' indicates that a write is in progress, and a '0' that no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. It, too, is read-only. Figure 7. RDSR: Read Status Register Sequence
S 0 C INSTRUCTION D 1 2 3 4 5 6 7 8
Its value can only be changed by one of the events listed in the previous paragraph, or as a result of executing WREN or WRDI instruction. It cannot be changed using a WRSR instruction. A '1' indicates that the latch is set (the forthcoming Write instruction will be executed), and a '0' that it is reset (and any forthcoming Write instructions will be ignored). The Block Protect (BP0 and BP1) bits indicate the amount of the memory that is to be writeprotected. These two bits are non-volatile. They are set using a WRSR instruction. During a Write operation (whether it be to the memory area or to the status register), all bits of the status register remain valid, and can be read using the RDSR instruction. However, during a Write operation, the values of the non-volatile bits (SRWD, BP0, BP1) become frozen at a constant value. The updated value of these bits becomes available when a new RDSR instruction is executed, after completion of the write cycle. On the other hand, the two read-only bits (WEL, WIP) are dynamically updated during internal write cycles. Using this facility, it is possible to poll the WIP bit to detect the end of the internal write cycle. Write Status Register (WRSR) The format of the WRSR instruction is shown in Figure 8. After the instruction and the eight bits of the status register have been latched-in, the internal Write cycle is triggered by the rising edge of the S line. This must occur before the rising edge of the 17th clock pulse (as indicated in Figure 14), otherwise the internal write sequence is not performed. The WRSR instruction is used for the following: s to select the size of memory area that is to be write-protected
s
to select between SPM (Software Protected Mode) and HPM (Hardware Protected Mode).
9 10 11 12 13 14 15
STATUS REG. OUT HIGH IMPEDANCE Q 7 MSB 6 5 4 3 2 1 0 7 MSB
STATUS REG. OUT 6 5 4 3 2 1 0 7 MSB
AI02031
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M95256, M95128
Table 6. Write Protected Block Size
Status Register Bits Protected Block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95256 none 6000h - 7FFFh 4000h - 7FFFh 0000h - 7FFFh M95128 none 3000h - 3FFFh 2000h - 3FFFh 0000h - 3FFFh Array Addresses Protected
The size of the write-protection area applies equally in SPM and HPM. The BP1 and BP0 bits of the status register have the appropriate value (see Table 6) written into them after the contents of the protected area of the EEPROM have been written. The initial delivery state of the BP1 and BP0 bits is 00, indicating a write-protection size of 0. Software Protected Mode (SPM) The act of writing a non-zero value to the BP1 and BP0 bits causes the Software Protected Mode (SPM) to be started. All attempts to write a byte or page in the protected area are ignored, even if the Write Enable Latch is set. However, writing is still allowed in the unprotected area of the memory array and to the SRWD, BP1 and BP0 bits of the status register, provided that the WEL bit is first set. Hardware Protected Mode (HPM) The Hardware Protected Mode (HPM) offers a higher level of protection, and can be selected by setting the SRWD bit after pulling down the W pin or by pulling down the W pin after setting the SRWD bit. The SRWD is set by the WSR instruction, provided that the WEL bit is first set. Figure 8. WRSR: Write Status Register Sequence
The setting of the SRWD bit can be made independently of, or at the same time as, writing a new value to the BP1 and BP0 bits. Once the device is in the Hardware Protected Mode, the data bytes in the protected area of the memory array, and the content of the status register, are write-protected. The only way to reenable writing new values to the status register is to pull the W pin high. This cause the device to leave the Hardware Protected Mode, and to revert to being in the Software Protected Mode. (The value in the BP1 and BP0 bits will not have been changed). Further details of the operation of the Write Protect pin (W) is given earlier, on page 3. Typical Use of HPM and SPM The W pin can be dynamically driven by an output port of a microcontroller. It is also possible, though, to connect it permanently to V SS (by a solder connection, or through a pull-down resistor). The manufacturer of such a printed circuit board can take the memory device, still in its initial delivery state, and can solder it directly on to the board. After power on, the microcontroller can be instructed to write the protected data into the
S 0 C INSTRUCTION STATUS REG. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D HIGH IMPEDANCE Q
7 MSB
6
5
4
3
2
1
0
AI02282
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M95256, M95128
Figure 9. Read EEPROM Array Operation Sequence
S 0 C INSTRUCTION 16 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
D HIGH IMPEDANCE Q
15 14 13
3
2
1
0 DATA OUT 7 MSB
AI01793
6
5
4
3
2
1
0
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don't Care.
Table 7. Address Range Bits
Device Address Bits M95256 A14-A0 M95128 A13-A0
Note: 1. b15 is Don't Care on the M95256 series. b15 and b14 are Don't Care on the M95128 series.
appropriate area of the memory. When it has finished, the appropriate values are written to the BP1, BP0 and SRWD bits, thereby putting the device in the hardware protected mode. An alternative method is to write the protected data, and to set the BP1, BP0 and SRWD bits, before soldering the memory device to the board. Again, this results in the memory device being placed in its hardware protected mode. If the W pin has been connected to V SS by a pulldown resistor, the memory device can be taken
out of the hardware protected mode by driving the W pin high, to override the pull-down resistor. If the W pin has been directly soldered to V SS, there is only one way of taking the memory device out of the hardware protected mode: the memory device must be de-soldered from the board, and connected to external equipment in which the W pin is allowed to be taken high. Read Operation The chip is first selected by holding S low. The serial one byte read instruction is followed by a two byte address (A15-A0), each bit being latched-in during the rising edge of the clock (C). The data stored in the memory, at the selected address, is shifted out on the Q output pin. Each bit is shifted out during the falling edge of the clock (C) as shown in Figure 9. The internal address counter is automatically incremented to the next higher address after each byte of data has been shifted out. The data stored in the memory, at the
Figure 10. Write Enable Latch Sequence
S 0 C INSTRUCTION D HIGH IMPEDANCE Q
AI02281B
1
2
3
4
5
6
7
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M95256, M95128
Figure 11. Byte Write Operation Sequence
S 0 C INSTRUCTION 16 BIT ADDRESS DATA BYTE 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D HIGH IMPEDANCE Q
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
AI01795
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don't Care.
next address, can be read by successive clock pulses. When the highest address is reached, the address counter rolls over to "0000h", allowing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip. The chip can be deselected at any time during data output. If a read instruction is received during
a write cycle, it is rejected, and the memory device deselects itself. Byte Write Operation Before any write can take place, the WEL bit must be set, using the WREN instruction. The write state is entered by selecting the chip, issuing three
Figure 12. Page Write Operation Sequence
S 0 C INSTRUCTION 16 BIT ADDRESS DATA BYTE 1 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C DATA BYTE 2 DATA BYTE 3 DATA BYTE N
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
AI01796
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don't Care.
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M95256, M95128
bytes of instruction and address, and one byte of data. Chip Select (S) must remain low throughout the operation, as shown in Figure 11. The product must be deselected just after the eighth bit of the data byte has been latched in, otherwise the write process is cancelled. As soon as the memory device is deselected, the self-timed internal write cycle is initiated. While the write is in progress, the status register may be read to check the status of the SRWD, BP1, BP0, WEL and WIP bits. In particular, WIP contains a `1' during the self-timed write cycle, and a `0' when the cycle is complete, (at which point the write enable latch is also reset). Page Write Operation A maximum of 64 bytes of data can be written during one Write time, tW, provided that they are all to the same page (see Figure 6). The Page Write operation is the same as the Byte Write operation, except that instead of deselecting the device after the first byte of data, up to 63 additional bytes can be shifted in (and then the device is deselected after the last byte). Any address of the memory can be chosen as the first address to be written. If the address counter reaches the end of the page (an address of the form xxxx xx11 1111) and the clock continues, the counter rolls over to the first address of the same page (xxxx xx00 0000) and over-writes any previously written data. As before, the Write cycle only starts if the S transition occurs just after the eighth bit of the last data byte has been received, as shown in Figure 12. Table 8. Initial Status Register Format
b7 0 0 0 0 0 0 0 b0 0
DATA PROTECTION AND PROTOCOL SAFETY To protect the data in the memory from inadvertent corruption, the memory device only responds to correctly formulated commands. The main security measures can be summarized as follows: - The WEL bit is reset at power-up. - S must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile write cycle (in the memory array or in the status register). - Accesses to the memory array are ignored during the non-volatile programming cycle, and the programming cycle continues unaffected. - After execution of a WREN, WRDI, or RDSR instruction, the chip enters a wait state, and waits to be deselected. - Invalid S and HOLD transitions are ignored. POWER ON STATE After power-on, the memory device is in the following state: - low power stand-by state - deselected (after power-on, a high-to-low transition is required on the S input before any operations can be started). - not in the hold condition - the WEL bit is reset - the SRWD, BP1 and BP0 bits of the status register are un-changed from the previous power-down (they are non-volatile bits). INITIAL DELIVERY STATE The device is delivered with the memory array in a fully erased state (all data set at all "1's" or FFh). The status register bits are initialized to 00h, as shown in Table 8.
Table 9. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Output Load 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC CL = 100 pF
Figure 13. AC Testing Input Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
Note: 1. Output Hi-Z is defined as the point where data is no longer driven.
Table 10. Input Parameters1 (TA = 25 C, f = 5 MHz)
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition Min. Max. 8 6 Unit pF pF
Note: 1. Sampled only, not 100% tested.
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M95256, M95128
Table 11. DC Characteristics (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; VCC = 4.5 to 5.5 V) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.5 to 5.5 V) (TA = 0 to 70 C or -20 to 85 C; VCC = 1.8 to 3.6 V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Voltage Range all all 4.5-5.5 4.5-5.5 ICC Supply Current 2.7-3.6 2.5-5.5 1.8-3.6 4.5-5.5 ICC1 Supply Current (Stand-by) 4.5-5.5 2.7-3.6 2.5-5.5 1.8-3.6 VIL VIH Input Low Voltage Input High Voltage all all 4.5-5.5 VOL1 Output Low Voltage 4.5-5.5 2.7-3.6 2.5-5.5 1.8-3.6 4.5-5.5 VOH1 Output High Voltage 4.5-5.5 2.7-3.6 2.5-5.5 1.8-3.6 6 6 5 6 3 6 6 5 all all 6 3 6 6 5 6 3 6 6 5 IOL = 2 mA, VCC = 5 V IOL = 2 mA, VCC = 5 V IOL = 1.5 mA, VCC = 2.7 V IOL = 1.5 mA, VCC = 2.5 V IOL = 0.15 mA, VCC = 1.8 V IOH = -2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V IOH = -0.4 mA, VCC = 2.7 V IOH = -0.4 mA, VCC = 2.5 V IOH = -0.1 mA, VCC = 1.8 V 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC Temp. Range all all 6 3 C = 0.1 VCC/0.9. VCC at 5 MHz, VCC = 5 V, Q = open C = 0.1 VCC/0.9. VCC at 2 MHz, VCC = 5 V, Q = open C = 0.1 VCC/0.9. VCC at 5 MHz, VCC = 2.7 V, Q = open C = 0.1 V CC/0.9. VCC at 2 MHz, VCC = 2.5 V, Q = open C = 0.1 V CC/0.9. VCC at 1 MHz, VCC = 1.8 V, Q = open S = VCC, VIN = VSS or VCC , VCC = 5 V S = VCC, VIN = VSS or VCC , VCC = 5 V S = VCC, VIN = VSS or VCC , VCC = 2.7 V S = VCC, VIN = VSS or VCC , VCC = 2.5 V S = VCC, VIN = VSS or VCC , VCC = 1.8 V - 0.3 0.7 VCC Test Condition Min. Max. 2 2 4 4 3 2 2 10 20 2 2 1 0.3 VCC VCC+1 0.4 0.4 0.4 0.4 0.3 Unit A A mA mA mA mA mA A A A A A V V V V V V V V V V V V
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
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M95256, M95128
Table 12A. AC Characteristics
M95256 / M95128 Symbol Alt. Parameter VCC=4.5 to 5.5 V VCC=4.5 to 5.5 V TA=0 to 70C or TA=-40 to 125C -40 to 85C Min fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tDLDH 2 tDHDL 2 tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW tDIS tV tHO tRO tFO tLZ tHZ tWC tCLH tCLL tRC tFC tDSU tDH tRI tFI fSCK tCSS1 tCSS2 tCS tCSH Clock Frequency S Active Setup Time S Not Active Setup Time S Deselect Time S Active Hold Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Data In Rise Time Data In Fall Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time 0 50 50 50 100 10 70 40 60 60 100 60 0 100 100 100 250 10 20 30 1 1 140 90 120 120 250 150 D.C. 90 90 100 90 90 90 90 1 1 40 50 1 1 Max 5 Min D.C. 200 200 200 200 200 200 200 1 1 Max 2 MHz ns ns ns ns ns ns ns s s ns ns s s ns ns ns ns ns ns ns ns ns ns ns ms Unit
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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M95256, M95128
Table 12B. AC Characteristics
M95256-V / M95128-V Symbol Alt. Parameter M95256-W / M95128-W M95256-R / M95128-R Unit
VCC= VCC= VCC= 2.7 to 3.6 V 2.5 to 5.5 V 1.8 to 3.6 V TA=0 to 70C TA=0 to 70C TA=0 to 70C or -40 to 85C or -40 to 85C or -20 to 85C Min Max 5 Min D.C. 200 200 200 200 200 200 200 0.05 0.05 20 30 0.05 0.05 70 40 60 60 100 60 0 50 50 50 100 10 0 100 100 100 250 10 140 90 120 120 250 150 0 200 200 250 500 10 40 50 1 1 350 200 250 250 500 380 1 1 60 100 1 1 Max 2 Min D.C. 400 400 300 400 400 400 400 1 1 Max 1
fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH 1 tCL 1 tCLCH 2 tCHCL 2 tDVCH tCHDX tDLDH 2 tDHDL 2 tHHCH tHLCH tCHHL tCHHH tSHQZ 2 tCLQV tCLQX tQLQH 2 tQHQL 2 tHHQX 2 tHLQZ 2 tW
fSCK
Clock Frequency
D.C. 90 90 100 90 90 90 90
MHz ns ns ns ns ns ns ns s s ns ns s s ns ns ns ns ns ns ns ns ns ns ns ms
tCSS1 S Active Setup Time tCSS2 S Not Active Setup Time tCS tCSH S Deselect Time S Active Hold Time S Not Active Hold Time tCLH tCLL tRC tFC tDSU tDH tRI tFI Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Data In Rise Time Data In Fall Time Clock Low Hold Time after HOLD not Active Clock Low Hold Time after HOLD Active Clock High Set-up Time before HOLD Active Clock High Set-up Time before HOLD not Active tDIS tV tHO tRO tFO tLZ tHZ tWC Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Time
Note: 1. tCH + tCL 1 / fC. 2. Value guaranteed by characterization, not 100% tested in production.
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M95256, M95128
Figure 14. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
HIGH IMPEDANCE
AI01447
Figure 15. Hold Timing
S tHLCH tCHHL C tCHHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI02032
Figure 16. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCL
tSHQZ
LSB OUT
AI01449B
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M95256, M95128
Table 13. Ordering Information Scheme
Example: M95256 - R MW 6 T
Memory Capacity 256 128 256 Kbit (32K x 8) 128 Kbit (16K x 8) T
Option Tape and Reel Packing
Temperature Range 11 5 Operating Voltage blank 4.5 V to 5.5 V V W R
3
0 C to 70 C -20 C to 85 C -40 C to 85 C -40 C to 125 C
6 32
2.7 V to 3.6 V 2.5 V to 5.5 V 1.8 V to 3.6 V BN MW MN DL
4
Package PSDIP8 (0.25 mm frame) SO8 (200 mil width) SO8 (150 mil width) TSSOP14 (169 mil width)
5
Note: 1. 2. 3. 4. 5.
Temperature range available only on request. Produced with High Reliability Certified Flow (HRCF), in VCC range 4.5 V to 5.5 V only. The -R version (VCC range 1.8 V to 3.6 V) only available in temperature ranges 5 or 1. SO8, 150 mil width, package is available for the M95128 series only. TSSOP14, 169 mil width, package is available for the M95128 series only.
ORDERING INFORMATION The notation used for the device number is as shown in Table 13. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M95256, M95128
Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min. 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max. 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ. Min. 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max. 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 inches
Figure 17. PSDIP8 (BN)
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Note: 1. Drawing is not to scale.
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M95256, M95128
Table 15. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 18. SO8 narrow (MN)
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Drawing is not to scale.
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M95256, M95128
Table 16. SO8 - 8 lead Plastic Small Outline, 200 mils body width
mm Symb. Typ. A A1 A2 B C D E e H L N CP 1.27 0.20 0.35 - 5.15 5.20 - 7.70 0.50 0 8 0.10 0.10 Min. Max. 2.03 0.25 1.78 0.45 - 5.35 5.40 - 8.10 0.80 10 0.050 0.008 0.014 - 0.203 0.205 - 0.303 0.020 0 8 0.004 0.004 Typ. Min. Max. 0.080 0.010 0.070 0.018 - 0.211 0.213 - 0.319 0.031 10 inches
Figure 19. SO8 wide (MW)
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: 1. Drawing is not to scale.
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M95256, M95128
Table 17. TSSOP14 - 14 lead Thin Shrink Small Outline
mm Symb. Typ. A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 4.90 6.25 4.30 - 0.50 0 14 0.08 Min. Max. 1.10 0.15 0.95 0.30 0.20 5.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.193 0.246 0.169 - 0.020 0 14 0.003 Typ. Min. Max. 0.043 0.006 0.037 0.012 0.008 0.197 0.256 0.177 - 0.028 8 inches
Figure 20. TSSOP14 (DL)
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
B
e TSSOP
Note: 1. Drawing is not to scale.
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M95256, M95128
Table 18. Revision History
Date 17-Nov-1999 07-Feb-2000 22-Feb-2000 15-Mar-2000 Description of Revision New -V voltage range added (including the tables for DC characteristics, AC characteristics, and ordering information). New -V voltage range extended to M95256 (including AC characteristics, and ordering information). tCLCH and tCHCL, for the M95xxx-V, changed from 1us to 100ns -V voltage range changed to 2.7-3.6V
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M95256, M95128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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